Nanolasers Innovations and Patents


© 2002, XQ23.COM Research

3D
ADSL
ANOVA
ATM
ActiveX
Active Channels
Algorithms
Analysis of Variance
Artificial Intelligence
Artificial Life
Asynchronous processing
Augmented Reality
Belief Networks
Biometrics
Bulletin Board Systems
C Programming
Clustering
Computer
Computer Architecture
Computer Chips
Computer Consulting
Computer Games
Computer Gaming
Computer Memory
Computer Networks
Computer Program
Computer Programming
Computer Science
Computer code
Control circuits
Data Analysis
Data Communication
Data Communications
Data Formats
Data Links
Data Mining
Data Storage
Data encoding
Data interchange
Data processing
Database Architecture
Database Design
Database Programming
Database Software
Desktop Publishing
Digital Keys
Distributed Computing
Dynamic classification
Dynamic configuration
Dynamic software
E-Books
Electronic equipment
Emulators
Error Handling
Error correcting codes
Ethernet
Genetic Programming
Haptics
Hierarchial documents
High Datga Rate
Home Automation
Human-Computer Interaction
Image Compression
Information processing
Integrated Circuits
Integrated Software
Integrated circuit design
JPEG
Java
Knowledge Representation
Linux
Local Networking
MPEG
Machine Learning
Memory Arrays
Memory Chips
Mobile Computing
Multiprocessors
MySQL
Nanolasers
Natural Language
Network Access
Network Area
Network Routers
Network Switches
Neural Networks
Object-based programming
Open Source
Optical Waveguides
Parallel Processing
Photonic Crystals
Photonics
Postgress
Regression Trees
Remote Networking
Search Trees
Shared memory
Signal Analysis
Signal Processing
Software Architecture
Software Integration
Software Layout
Software Methods
Software Testing
Software management
Software program
Software tools
Speech Recognition
Supercomputers
Supercomputing
Supervised Learning
Testing Devices
Video streaming
Video system
Virtual Reality
Wavelet Compression
Wavelets
active matrix
analog controls
asynchronous communication
audio compression
authentication
bandwidth
fractal compression
rech1
video compression



More information on:  Nanolasers and   Nanolasers Research References.

Recent U.S. patents related to Nanolasers:

1:
6,272,493: System and method for facilitating a windows based content manifestation environment within a WWW browser
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6,381,669: Multi-bank, fault-tolerant, high-performance memory addressing system and method
6,381,628: Summarized application profiling and quick network profiling
6,378,066: Method, apparatus, and article of manufacture for developing and executing data flow programs, and optimizing user input specifications
6,377,980: Methods and apparatus for a directory-less memory access protocol in a distributed shared memory computer system
6,374,329: High-availability super server
6,374,285: Method for mutual exclusion of locks in a remote-write globally ordered network of processors
6,370,625: Method and apparatus for lock synchronization in a microprocessor system
6,370,622: Method and apparatus for curious and column caching
6,370,615: Method and system for coherently caching I/O devices across a network
6,370,550: Control of multimedia information in audio/video/data system
6,370,145: Internet switch router
6,366,911: Partitioning of sorted lists (containing duplicate entries) for multiprocessors sort and merge
6,366,902: Using an epoch number to optimize access with rowid columns and direct row access
6,363,453: Parallel processor with redundancy of processor pairs
6,363,389: Technique for creating a unique quasi-random row identifier
6,360,302: Method and system for dynamically changing page types in unified scalable shared-memory architectures
6,360,297: System bus read address operations with data ordering preference hint bits for vertical caches
6,359,886: Method and apparatus for filtering and routing communications frames
6,357,041: Data-centric multi-level blocking
6,354,861: Data processing system component alignment
6,353,898: Resource management in a clustered computer system
6,353,875: Upgrading of snooper cache state mechanism for system bus with read/castout (RCO) address transactions
6,351,795: Selective address translation in coherent memory replication
6,351,790: Cache coherency mechanism
6,349,367: Method and system for communication in which a castout operation is cancelled in response to snoop responses
6,349,366: Method and apparatus for developing multiprocessor cache control protocols using a memory management system generating atomic probe commands and system data control response commands
6,349,360: System bus read address operations with data ordering preference hint bits
6,349,038: EMC characteristics of a printed circuit board
RE37,552: System and method for power-efficient charging and discharging of a capacitive load from a single source
6,347,000: 35 6,345,321
6,343,347: Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transaction
6,343,346: Cache coherent network adapter for scalable shared memory processing systems
6,343,344: System bus directory snooping mechanism for read/castout (RCO) address transaction
6,343,293: Storing the uncompressed data length in a LOB map to speed substring access within a LOB value
6,343,286: Efficient technique to defer large object access with intermediate results
6,341,339: Apparatus and method for maintaining data coherence within a cluster of symmetric multiprocessors
6,339,840: Apparatus and method for parallelizing legacy computer code
6,338,146: Method and apparatus for fault-tolerant, scalable and non-blocking three-phase flushing for committing database transactions in a cluster of multiprocessors
6,338,124: Multiprocessor system bus with system controller explicitly updating snooper LRU information
6,338,112: Resource management in a clustered computer system
6,338,063: Method and computer program product for reducing lock contention in a multiple instruction execution stream processing environment
6,336,191: Method and system for clock compensation in instruction level tracing in a symmetrical multi-processing system
6,336,177: Method, system and computer program product for managing memory in a non-uniform memory access system
6,335,930: Multi-stage interconnection network for high speed packet switching
6,332,185: Method and apparatus for paging data and attributes including an atomic attribute for digital data processor
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: transformation based upon type constraint analysis
6,230,197: Method and apparatus for rules-based storage and retrieval of multimedia interactions within a communication center
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