Recent U.S. patents related to Integrated circuit design:
6,381,730: Method and system for extraction of parasitic interconnect impedance including inductance
6,381,717: Snoopy test access port architecture for electronic circuits including embedded core having test access port with instruction driven wake-up
6,381,704: Method and apparatus for altering timing relationships of non-overlapping clock signals in a microprocessor
6,380,598: Radiation hardened semiconductor memory
6,380,010: Shielded channel transistor structure with embedded source/drain junctions
6,379,867: Moving exposure system and method for maskless lithography system
6,379,848: Reticle for use in photolithography and methods for inspecting and making same
6,378,115: LSI manufacturing method and recording medium for storing layout software
6,378,114: Method for the physical placement of an integrated circuit adaptive to netlist changes
6,378,110: Layer-based rule checking for an integrated circuit layout
6,378,109: Method of simulation for gate oxide integrity check on an entire IC
6,378,090: Hierarchical test access port architecture for electronic circuits including embedded core having built-in test access port
6,377,912: Emulation system with time-multiplexed interconnect
6,377,315: System and method for providing a low power receiver design
6,377,197: DAC gain compensation for temperature and process variations
6,377,130: Temperature stabilized CMOS oscillator circuit
6,374,398: Efficient database for die-per-wafer computations
6,374,043: Fully-integrated VCM driver with controlled and predictable Class-AB linear operation
6,374,020: Method and apparatus for optically interconnecting a plurality of devices
6,374,003: Method and apparatus for optically modulating light through the back side of an integrated circuit die using a plurality of optical beams
6,373,975: Error checking of simulated printed images with process window effects included
6,373,908: Adaptive electronic transmission signal cancellation apparatus for full duplex communication
6,373,114: Barrier in gate stack for improved gate dielectric integrity
6,373,112: Polysilicon-germanium MOSFET gate electrodes
6,372,633: Method and apparatus for forming metal interconnects
6,372,586: Method for LDMOS transistor with thick copper interconnect
6,370,679: Data hierarchy layout correction and verification method and apparatus
6,370,677: Method and system for maintaining hierarchy throughout the integrated circuit design process
6,370,675: Semiconductor integrated circuit design and evaluation system using cycle base timing
6,370,673: Method and system for high speed detailed placement of cells within an integrated circuit design
6,370,661: Apparatus for testing memory in a microprocessor
6,370,575: Web-based status/issue tracking system based on parameterized definition
6,370,492: Modified design representation for fast fault simulation of an integrated circuit
6,370,046: Ultra-capacitor based dynamically regulated charge pump power converter
6,369,427: Integrated circuitry, interface circuit of an integrated circuit device, and cascode circuitry
6,368,933: Tap connections for circuits with leakage suppression capability
6,368,922: Internal ESD protection structure with contact diffusion
6,368,902: Enhanced efuses by the local degradation of the fuse link
6,367,062: System and method for detecting an excessive number of series-connected pass FETs
6,367,060: Method and apparatus for clock tree solution synthesis based on design constraints
6,367,059: Carry chain standard cell with charge sharing reduction architecture
6,367,056: Method for incremental timing analysis
6,367,055: Method and apparatus for determining certain characteristics of circuit elements
6,367,051: System and method for concurrent buffer insertion and placement of logic gates
6,366,973: Slave interface circuit for providing communication between a peripheral component interconnect (PCI) domain and an advanced system bus (ASB)
6,366,513: Reduction of noise in memory integrated circuits with dedicate power supply bus and ground bus for sense amplifiers
6,366,131: System and method for increasing a drive signal and decreasing a pin count
6,365,954: Metal-polycrystalline silicon-n-well multiple layered capacitor
6,365,482: I.C. thin film resistor stabilization method
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